We’re Exhibiting at EDS 2025

The Engineering Design Show, 8 – 9 October 2025, Coventry Building Society Arena, UK, Stand J3

  • InterFET

SMP4118A

InterFET Product Image (SOT-23)
InterFET SMP4118A N-Channel JFET with N0001H Geometry. Maximum leakage of -1pA and a low input capacitance of 3pF (max). All of this in a SOT-23 package.
  • Compliant
  • InterFET

2N4118A

InterFET Product Image (TO-72)
InterFET 2N4118A N-Channel JFET with N0001H Geometry. Maximum leakage of -1pA and a low input capacitance of 3pF (max). All of this in a TO-72 package.
  • Compliant

SMP4118A

InterFET SMP4118A N-Channel JFET with N0001H Geometry. Maximum leakage of -1pA and a low input capacitance of 3pF (max). All of this in a SOT-23 package.

2N4118A

InterFET 2N4118A N-Channel JFET with N0001H Geometry. Maximum leakage of -1pA and a low input capacitance of 3pF (max). All of this in a TO-72 package.